Field of the Invention
The present invention relates to integrated circuits (ICs), and in particular to a wafer-level chip scale package (WLCSP) with a redistribution layer and a method of manufacturing the same.
Description of the Related Art
The desire to make electronic products small, lightweight, and high-performing has developed into a desire to make electronic parts small, lightweight, and high-performing. This desire has caused developments to proceed in various packaging technologies, along with developments in the technologies related to designing and manufacturing semiconductors. Representative examples of packaging technologies include the ball grid array (BGA), the flip-chip, and the chip scale package (CSP) based on area array and surface-mount packaging.
Among the above, the CSP is a packaging technology that enables a small package to be the same size as the real chip to be developed. In particular, in a Wafer-level chip scale package (WLCSP), the packaging is performed in a wafer level so that the packaging costs per chip can be remarkably reduced. Typically, the WLCSP includes a redistribution layer (RDL) wiring traces, an under bump metallurgy (UBM) layer forming a bump, and a passivation layer protecting a circuit.